1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more specifically, to a semiconductor device and a method for fabricating an element isolating portion between two or more field effect transistors (FETs) which are semiconductor elements formed on a semi-insulating substrate.
2. Description of the Related Art
A compound semiconductor FET made of a compound such as GaAs or the like is widely used for both digital and analog integrated circuits. Since a compound semiconductor such as GaAs or the like has a higher electron mobility than that of a Si semiconductor, the compound semiconductor FET has an advantage of having a high operation speed suitable for a device which operates in the range from a microwave to a millimeter wave and a high output device. Furthermore, in the case where a compound semiconductor such as GaAs or the like is used as a material of a semi-insulating substrate, the compound semiconductor FET has an advantage of realizing a lower parasitic capacitance than that obtained when using Si as a material of the substrate, and thus reducing an influence on the device.
One example of integrated circuits using a compound semiconductor is a chip used as an amplifier incorporated in a portable phone. Usually, two or more FETs are used in one chip in order to obtain an amplified voltage at a high efficiency and at a high output level. In this chip, a scribe line portion is provided as a result of subscribing a semi-insulating substrate so as to surround the FETs. Moreover, an element isolating portion is provided between the FETs which are placed apart from one another. The element isolating portion is required in order to prevent an interference and an oscillation occurring between FETS. Japanese Laid-Open Publication No. 5-275474, for example, proposes forming a groove reaching a semi-insulating substrate from a surface of a chip between two adjacent FETs.
Hereinafter, an element isolating portion and a scribe line portion of a conventional semiconductor device 600, and a method for forming the portions will be described with reference to FIG. 6.
FIG. 6 shows cross-sectional views illustrating steps of a method for forming an element isolating portion 69 and a scribe line portion 70 of the conventional semiconductor device 600. In FIG. 6, parts A1 to A5 show steps of forming the element isolating portion 69, and parts B1 to B5 show steps of forming the scribe line portion 70. Parts A1, A2, A3, A4 and A5 and parts B1, B2, B3, B4 and B5 show corresponding steps, respectively.
As shown in parts A5 and B5 in FIG. 6, the conventional semiconductor device 600 includes a semi-insulating substrate 65; a buffer layer 64 provided on the semi-insulating substrate 65; an interlevel film 63 provided on the buffer layer 64; an electrode 62 provided on the interlevel film 63; and a protective film 61 provided on the buffer layer 64 covering ends of the electrode 62 and the interlevel film 63, and formed so that a top surface of the electrode 62 is partially exposed so as to form electrode windows 66. The semi-insulating substrate 65 is made of GaAs, and the buffer layer 64 includes an undoped GaAs film (thickness: 5000 .ANG.), an undoped Al.sub.0.2 Ga.sub.0.8 As film (thickness: 2000 .ANG.), and an undoped GaAs film (thickness: 1000 .ANG.) sequentially provided in this order from the bottom. The interlevel film 63 includes an upper layer made of SiN having a thickness of 5000 .ANG. and a lower layer made of SiO.sub.2 having a thickness of 5000 .ANG.. The electrode 62 is made of Au, and the protective film 61 is made of SiN having a thickness of 5000 .ANG.. As shown in part A5 in FIG. 6, the semiconductor device 600 has the element isolating portion 69 penetrating the buffer layer 64 and reaching an inside of the semi-insulating substrate 65. In the vicinity of the element isolating portion 69, the buffer layer 64 and the semi-insulating substrate 65 are exposed to outside air. Furthermore, as shown in part B5 in FIG. 6, the protective film 61 is partially disconnected on the buffer layer 64 so as to form the scribe line portion 70. In the vicinity of the scribe line portion 70, the buffer layer 64 is exposed to outside air.
The buffer layer 64 has a function of reducing a current leakage to the substrate 65 through a channel. The interlevel film 63 inactivates the surface of the buffer layer 64 so as to obtain the stability thereof, and prevents the buffer layer 64 from adsorbing molecules in the air.
Hereinafter, a conventional method for fabricating the semiconductor device 600 having the element isolating portion 69 and the scribe line portion 70 will be described in detail.
It should be noted that the conventional method for fabricating FETs will not be shown in drawings because it is known to those skilled in the art.
After forming the metal layers for a gate, a source and a drain on the active layer, the interlevel film 63 is formed so as to cover an active layer on the buffer layer 64. Subsequently, a contact hole is formed in the interlevel film 63 so as to reach the metal layer. Then, the electrode 62 is formed on the interlevel film 63 so as to fill the contact hole, thereby forming a FET. Any appropriate method can be employed in fabricating the FETs.
Then, a first resist layer 68-1 (parts A1 and B1 of FIG. 6) used for etching the interlevel film 63 is formed in a dark room by a resist coater. The first resist layer 68-1 has an opening having a width of 90 .mu.m at a position where the element isolating portion 69 will be formed and an opening having a width of 80 .mu.m at a position where the scribe line portion 70 will be formed.
Next, the interlevel film 63 including the SiN (upper) layer and the SiO.sub.2 (lower) layer is etched, as shown in parts A1 and B1 in FIG. 6, at positions where the element isolating portion 69 and the scribe line portion 70 will be formed. In this step, the SiN layer is etched by dry etching with CF.sub.4, and subsequently, the SiO.sub.2 layer is etched by wet etching with hydrofluoric acid. Then, the first resist layer 68-1 is removed by a resist remover. Thereafter, as shown in parts A2 and B2 in FIG. 6, a SiN layer is grown by plasma CVD on the buffer layer 64 covering the interlevel film 63 and the electrode 62 so as to form the protective film 61 having a thickness of 5000.ANG..
Subsequently, as shown in parts A3 and B3 in FIG. 6, a second resist layer 68-2 used for forming the electrode windows 66 functioning as a gate, a source and a drain of the FET on the Au electrode 62 is formed on the protective film 61 by a resist coater in a dark room. The second resist layer 68-2 has openings at positions where the electrode windows 66, the element isolating portion 69 and the scribe line portion 70 will be later formed. Next, still referring to parts A3 and B3 in FIG. 6, the protective film 61 is etched by dry etching with CF.sub.4 using the second resist layer 68-2 as a mask in order to form openings at positions where the element isolating portion 69 and the scribe line portion 70 will be formed. The second resist layer 68-2 has an opening having a width of 85 .mu.m at a position where the element isolating portion 69 will be formed and an opening having a width of 75 .mu.m at a position where the scribe line portion 70 will be formed. The width of each opening of the second resist layer 68-2 is slightly smaller than that of the first resist 68-1 because the protective film 61 needs to cover the interlevel film 63.
After removing the second resist layer 68-2 by a resist remover, a third resist layer 68-3 (part A4 and B4 in FIG. 6) used for forming the element isolating portion 69 is formed by a resist coater in a dark room. The third resist layer 68-3 has an opening having a width of 15 .mu.m at a position where the element isolating portion 69 will be formed. The resultant laminate is etched for about 10 minutes by wet etching using an etchant having a volume ratio of phosphoric acid to hydrogen peroxide to water of 4:1:5. As a result, a groove running from a top surface of the buffer layer 64 to an inside of the semi-insulating substrate 65 is formed. The groove has a depth "d" of as much as about 20 .mu.m.
In the case where the etching is not performed sufficiently deep to reach the inside of the semi-insulating substrate 65, the following problems occur. Since surfaces 64a of the buffer layer 64 facing a position where the element isolating portion 69 will be formed is exposed to outside air, impurities adsorbed on the surfaces 64a of the buffer layer 64 cause a current leakage between the FETs. In addition, the surface of the buffer layer 64 is oxidized due to a contact with outside air, resulting in causing a current leakage between the FETs. Therefore, in order to reduce the current leakage and improve electric characteristics of the chip, the etching is performed through the buffer layer 64 deep into the semi-insulating substrate 65 as described above.
Moreover, since wet etching is used in the etching step, the etching is performed not only along a direction perpendicular to but along to a direction horizontal to the semi-insulating substrate 65. Therefore, the buffer layer 64 is etched along the direction horizontal to the substrate 65 (i.e., side etching is performed) by a distance of as much as about 15 .mu.m as indicated by letter "s" in part A4 in FIG. 6, which is substantially equal to the width of the opening of the third resist layer 68-3.
Lastly, as shown in parts A5 and B5 in FIG. 6, the third resist layer 68-3 is removed by a resist remover. As a result, the semiconductor device 600 having the element isolating portion 69 and the scribe line portion 70 is produced.
The method for fabricating the conventional semi-conductor device as described above requires three steps of forming resist layers in a dark room until an element isolating portion is formed between the FETs in the case where two or more FETs (semiconductor elements) are formed in one chip. Therefore, the conventional method requires many steps.
In the chip fabricated in the conventional method, surfaces of the components defining the element isolating portion and the scribe line portion are exposed to outside air. AlGaAs used for making the buffer layer of the chip is likely to adsorb impurities in the air, and so is easily oxidized. Therefore, when the buffer layer is put into contact with outside air, AlGaAs is oxidized on the exposed surface of the buffer layer so that a current leaks to a channel region through the buffer layer.
Furthermore, the chip fabricated in the conventional method as described above has a groove having a depth of about 20 .mu.m and running deep inside of the semi-insulating substrate, the groove being formed as a result of etching. The groove is formed in order to reduce the current leakage due to impurities and oxidation of the surface of the buffer layer and to improve electric characteristics of the chip. As described above with reference to part A4 in FIG. 6, however, the etching causes side etching in both horizontal directions from the element isolating portion (2s=about 30 .mu.m). Therefore, in the conventional method, the width of the element isolating portion between the FETs should be prescribed considering such side etching. Accordingly, the conventional method has problems that the number of chips per wafer is small, and that a production efficiency is low.
In designing the chip as described above, it is important that the depth of the element isolating portion, as shown in part A5 in FIG. 6, should be designed so that the buffer layer made of undoped GaAs (5000 .ANG.), undoped Al.sub.0.2 Ga.sub.0.8 As (2000 .ANG.), and undoped GaAs (1000 .ANG.) is entirely removed in the corresponding area for the following reason. A specific resistance of the semi-insulating substrate is 10.sup.7 .OMEGA. cm or more, which is extremely high, while a specific resistance of the buffer layer is several or several tens .OMEGA. cm. When the element isolating portion is formed so as to reach the inside of the semi-insulating substrate having a high specific resistance, a conductivity between the FETs is sufficiently small so as to be negligible. Therefore, the current leakage can be effectively reduced and mutual interferences between the FETs do not substantially occur. Several tens of micrometers is sufficient for the length of element isolating portion, i.e., distance between the FETs in the direction horizontal to the semi-insulating substrate. When the FETs are arranged with such a distance therebetween, mutual interferences between the FETs do not substantially occur.